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construction
B：形状測定を使用した段差法
帯電したウェーハやレチクルの表面は微粒子を吸着（静電気吸着，ESA： electrostatic attraction）し，不良率を増やす｡
This Standard specifies the requirements for plating layers on leadframes intended for use at the upcoming inspection
SEMI E30-0703 (technical revision)
MF115200 - SEMI MF1152 - Test Method for Dimensions of Notches on Silicon Wafers Revision:SEMI MF1152-0316 - Superseded constructionWafers must be accurately aligned in various processing equipment during integrated circuit manufacture. A notch ground into the edge of the wafer at a specified orientation provides a positive method for such alignment. The accuracy of the critical dimensions of the notch controls the possible accuracy of the alignment. This Test Method may be used for process control, quality control, and incoming or outgoing inspection. Until an index of precision